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general description the MAX16952 is a current-mode, synchronous pwm step-down controller designed to operate with input volt- ages from 3.5v to 36v while using only 50a of quies- cent current at no load. the switching frequency is adjustable from 1mhz to 2.2mhz by an external resistor and can be synchronized to an external clock up to 2.4mhz. the MAX16952 output voltage is pin program- mable to be either 5v fixed, or adjustable from 1v to 10v. the wide input voltage range, along with its ability to operate in dropout during undervoltage transients, makes it ideal for automotive and industrial applications. the MAX16952 operates in fixed-frequency pwm mode and low quiescent current skip mode. it features an enable logic input, which is compatible up to 42v to dis- able the device and reduce its shutdown current to 10a. protection features include overcurrent limit, over- voltage, undervoltage, and thermal shutdown with auto- matic recovery. the device also features a power-good monitor to ease power-supply sequencing. the MAX16952 is available in a thermally enhanced 16-pin tssop package with an exposed pad, and is specified for operation over the -40c to +125c automo- tive temperature range. applications automotive industrial military point of load features wide 3.5v to 36v input voltage range 42v input transient tolerance high duty cycle during undervoltage transients 1mhz to 2.2mhz adjustable switching frequency adjustable (1v to 10v) output voltage with ?% accuracy three operating modes 50? ultra-low quiescent current skip mode forced fixed-frequency mode external frequency synchronization lowest bom count, current-mode control architecture power-good output enable input compatible from 3.3v logic level to 42v current-limit, thermal shutdown, and overvoltage protection -40? to +125? automotive temperature range automotive qualified 19-5789; rev 1; 10/12 MAX16952 36v, 2.2mhz step-down controller with low operating current for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maximintegrated.com. ordering information part temp range pin-package MAX16952aue/v+ -40c to +125c 16 tssop-ep* /v denotes an automotive qualified part. + denotes a lead(pb)-free/rohs-compliant package. * ep = exposed pad. typical operating circuit MAX16952 r fosc c l sgnd bias fb out cs c in fosc r comp r sense comp fsync en pgood c comp1 c comp2 c bst sup v bat dh bst nl nh pgnd dl l lx c out v out 5v evaluation kit available
MAX16952 36v, 2.2mhz step-down controller with low operating current 2 maxim integrated absolute maximum ratings electrical characteristics (v sup = v en = 14v, c in = 10f, c out = 94f, c bias = 2.2f, c bst = 0.1f, r fosc = 14.3k ? , t a = t j = -40c to +125c, unless otherwise noted. typical values are at t a = +25c.) (note 2) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. note 1: package thermal resistances were obtained using the method described in jedec specification jesd51-7, using a four-layer board. for detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial . sup and en to sgnd ............................................-0.3v to +42v lx to pgnd ..............................................................-1v to +42v bst to lx .................................................................-0.3v to +6v bias, fb, pgood, fsync to sgnd .......................-0.3v to +6v dh to lx ...................................................................-0.3v to +6v dl to pgnd .............................................-0.3v to (v bias + 0.3v) fosc to sgnd ........................................-0.3v to (v bias + 0.3v) cs and out to sgnd ............................................-0.3v to +11v pgnd to sgnd .....................................................-0.3v to +0.3v continuous power dissipation (t a = +70c) tssop (derate 26.1mw/c above +70c).......................2088.8mw operating temperature range .........................-40c to +125c junction temperature ......................................................+150c storage temperature range .............................-65c to +150c lead temperature (soldering, 10s) .................................+300c soldering temperature (reflow) .......................................+260c package thermal characteristics (note 1) tssop junction-to-ambient thermal resistance ( ja ) .........38.3c/w junction-to-case thermal resistance ( jc ) ...................3c/w parameter symbol conditions min typ max units sup input voltage range v sup (note 3) 3.5 36 v sup operating supply current i sup fixed 5v output, fixed-frequency, pwm mode, v fb = v bias , no external fets connected 1 ma skip mode supply current i skip no load, fixed 5v output 50 90 a sup shutdown supply current i shdn,sup v en = 0v 10 20 a v sup = 3.5v, i bias = 45ma 3.0 bias voltage v bias 6v < v sup < 36v 4.7 5.0 5.3 v bias undervoltage lockout v uvbias v bias rising 3.1 3.4 v bias undervoltage lockout hysteresis v bias falling 200 mv bias minimum load i bias(min) v sup - v bias > 200mv 45 ma output voltage (out) output voltage adjustable range 1.0 10 v out pulldown resistance r pull_d v en = 0v or fault condition active 30 output voltage (5v fixed mode) v out v sup = 6v to 36v, v fb = v bias , fixed-frequency mode (note 4) 4.925 5.0 5.075 v fb feedback voltage (adjustable mode) v fb v sup = 6v to 36v, 0v < (v cs - v out ) < 80mv, fixed-frequency mode 0.99 1.0 1.01 v fb current i fb v fb = 1.0v 0.02 a fb line regulation v en = v sup , 6v < v sup < 36v (note 4) 0.02 %/v
MAX16952 36v, 2.2mhz step-down controller with low operating current 3 maxim integrated parameter symbol conditions min typ max units transconductance (from fb to comp) g m,ea 1200 s error-amplifier output impedance r out,ea 30 m r fosc = 30.1k 1000 operating frequency f sw r fosc = 14.3k 1800 2000 2200 khz minimum on-time t on(min) 80 ns maximum fsync frequency f fsync(max) 2400 khz minimum fsync frequency f fsync(min) f fsync > 110% of internal frequency (20% duty cycle), f sw = 1000khz 1100 khz fsync logic-high threshold v fsync,hi 1.4 v fsync logic-low threshold v fsync,lo 0.4 v fsync internal pulldown resistance 1 m current limit cs input current i cs v cs = v out = 0v or v bias (note 5) -1 +1 a during normal operation 22 out input current i out v fb = v bias 32 a cs current-limit voltage threshold v limit v cs - v out , v bias = 5v, v out 2.5v 68 80 92 mv fault detection output overvoltage trip threshold v fb,ov v out = v fb , rising edge 108 113 118 %v fb output overvoltage trip hysteresis 2.5 % rising edge 25 output overvoltage fault propagation dela y t ovp falling edge 25 s output undervoltage trip threshold v fb,uv v out = v fb ; with respect to slewed fb threshold, falling edge 83 88 93 %v fb output undervoltage trip hysteresis 2.5 % falling edge 25 output undervoltage propagation dela y rising edge (excluding startup) 25 s pgood output low voltage v pgood,l i sink = 3ma 0.4 v pgood leakage current i pgood 1 a thermal shutdown threshold t shdn (note 5) +175 c thermal shutdown hysteresis (note 5) 15 c electrical characteristics (continued) (v sup = v en = 14v, c in = 10f, c out = 94f, c bias = 2.2f, c bst = 0.1f, r fosc = 14.3k ? , t a = t j = -40c to +125c, unless otherwise noted. typical values are at t a = +25c.) (note 2)
MAX16952 36v, 2.2mhz step-down controller with low operating current 4 maxim integrated parameter symbol conditions min typ max units gate drive (v bst - v lx ) forced to 5v 10 dh gate-driver on-resistance r dh (v bst - v lx ) forced to 0v 2 dl = high state 3.5 dl gate-driver on-resistance r dl dl = low state 2 dl rising 30 dh/dl dead time (note 5) t dead dh rising 30 ns bst input current i bst v lx = 0v, v bst = 5v, v dh - v lx = v dl - v pgnd = 0v 1 a bst on-resistance (note 5) 5 15 enable input en input threshold low v en,lo 1.2 v en input threshold high v en,hi 2.2 v en threshold voltage hysteresis 0.2 v en input current i en 0.5 a soft-start soft-start ramp time t ss 5 ms note 2: devices tested at t a = +25c. limits over temperature are guaranteed by design. note 3: for 3.5v operation, the n-channel mosfets threshold voltage should be compatible to (lower than) this input voltage. note 4: device not in dropout condition. note 5: guaranteed by design; not production tested. electrical characteristics (continued) (v sup = v en = 14v, c in = 10f, c out = 94f, c bias = 2.2f, c bst = 0.1f, r fosc = 14.3k ? , t a = t j = -40c to +125c, unless otherwise noted. typical values are at t a = +25c.) (note 2)
startup response (skip mode) MAX16952 toc01 10v/div 0v 0v 0v 0a 2v/div 2a/div 5v/div v sup v out i load v pgood 2ms/div 2.2mhz/3.3v startup response (skip mode) MAX16952 toc02 10v/div 2v/div 2a/div 5v/div v sup v out i load v pgood 2ms/div 2.2mhz/5v skip mode supply current vs. v sup MAX16952 toc03 v sup (v) i skip (a) 31 26 21 16 11 10 20 30 40 50 60 70 80 90 100 0 636 2.2mhz/5v pwm mode supply current vs. v sup MAX16952 toc04 v sup (v) i pwm (ma) 31 26 21 16 11 10 20 30 40 50 60 70 80 90 100 0 636 2.2mhz/5v efficiency vs. load current MAX16952 toc05 load current (a) efficiency (%) 3.5 3.0 2.0 2.5 1.0 1.5 0.5 10 20 30 40 50 60 70 80 90 100 0 0 4.0 v out = 5v v out = 3.3v fixed-frequency mode efficiency vs. load current maxa16952 toc06 load current (a) efficiency (%) 1 0.1 0.01 0.001 10 20 30 40 50 60 70 80 90 100 0 0.0001 10 skip mode v out = 5v v out = 3.3v switching frequency vs. r fosc MAX16952 toc07 r fosc (k i ) swithcing frequency (mhz) 35 30 25 20 15 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 1.0 10 40 typical operating characteristics (v sup = v en = 14v, c in = 47f, c out = 94f, c bias = 2.2f, c bst = 0.1f, r fosc = 13k ? , v fb = v bias , r bst = 75 ? , t a = +25c, unless otherwise noted.) MAX16952 36v, 2.2mhz step-down controller with low operating current 5 maxim integrated
load transient (pwm mode) MAX16952 toc08 500mv/div 2a/div 0a v out (ac-coupled) i load 100s/div 2.2mhz/5v load transient (pwm mode) MAX16952 toc09 200mv/div 2a/div 0a v out (ac-coupled) i load 100s/div 2.2mhz/3.3v synchronization with external signal at fsync MAX16952 toc10 10v/div 2v/div 0v 0v v lx v fsync (external signal at fsync) 400ns/div cold crank test (pwm mode) MAX16952 toc11 5v/div 0v 0v 0v 0a 5v/div 5v/div 5v/div v sup v out i load v pgood 10ms/div 2.2mhz/5v load dump test (skip mode) MAX16952 toc12 20v/div 0v 0v 0v 5v/div 5v/div v sup v out v pgood 100ms/div 2.2mhz/5v load dump test (pwm mode) MAX16952 toc13 20v/div 0v 0v 0v 2v/div 5v/div v sup v out v pgood 100ms/div 2.2mhz/5v typical operating characteristics (continued) (v sup = v en = 14v, c in = 47f, c out = 94f, c bias = 2.2f, c bst = 0.1f, r fosc = 13k ? , v fb = v bias , r bst = 75 ? , t a = +25c, unless otherwise noted.) MAX16952 36v, 2.2mhz step-down controller with low operating current 6 maxim integrated
output response to slow ramp at sup (pwm mode) MAX16952 toc14 10v/div 0v 0v 0v 0v 5v/div 5v/div 10v/div v sup v out v lx v pgood 4s/div 2.2mhz/5v i load = 4a output response to slow ramp at sup (skip mode) MAX16952 toc15 0v 0v 0v 0v 10v/div 5v/div 10v/div 5v/div v sup 2.2mhz/5v i load = 0a v out v lx v pgood 4s/div short-circuit test (skip mode) MAX16952 toc16 0v 0a 0v 2v/div 5a/div 5v/div v out 2.2mhz/5v i lx v pgood 100s/div short-circuit test (skip mode) MAX16952 toc17 0v 0a 0v 2v/div 5a/div 5v/div v out 2.2mhz/3.3v i lx v pgood 100s/div load regulation (pwm mode) MAX16952 toc18 i load (a) v out (v) 3.5 3.0 2.5 2.0 1.5 1.0 0.5 4.7 4.8 4.9 5.0 5.1 5.2 4.6 04.0 2.2mhz/5v pwm mode -40c +125c +25c load regulation (skip mode) MAX16952 toc19 i load (a) v out (v) 3.5 3.0 2.5 2.0 1.5 1.0 0.5 4.7 4.8 4.9 5.0 5.1 5.2 4.6 0 4.0 2.2mhz/5v +25c +125c -40c v out vs. temperature MAX16952 toc20 temperature ( c) v out (v) 110 95 65 80 -10 5 20 35 50 -25 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5 4.5 -40 125 2.2mhz/5v skip mode/0a load pwm mode/4a load MAX16952 36v, 2.2mhz step-down controller with low operating current 7 maxim integrated typical operating characteristics (continued) (v sup = v en = 14v, c in = 47f, c out = 94f, c bias = 2.2f, c bst = 0.1f, r fosc = 13k ? , v fb = v bias , r bst = 75 ? , t a = +25c, unless otherwise noted.)
line regulation (pwm mode) MAX16952 toc21 v sup (v) v out (v) 31 26 21 16 11 4.70 4.80 4.90 5.00 5.10 5.20 4.60 636 +25c -40c +125c 2.2mhz/5v line regulation (skip mode) MAX16952 toc22 v sup (v) v out (v) 31 26 21 16 11 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5 4.5 636 -40c 2.2mhz/5v +25c +125c v bias vs. i bias MAX16952 toc23 i bais (ma) v bias (v) 90 80 70 60 50 40 30 20 10 4.4 4.6 4.8 5.0 5.2 4.2 0100 -40c +25c +125c 2.2mhz/5v shutdown current vs. v sup MAX16952 toc24 v sup (v) shutdown current (a) 33 30 24 27 9 12 15 18 21 6 2 4 6 8 10 12 14 16 18 20 0 336 shutdown current vs. temperature MAX16952 toc25 temperature (c) shutdown current (a) 110 95 80 65 50 35 20 5 -10 -25 10.35 10.40 10.45 10.50 10.55 10.60 10.30 -40 v sup = 14v v en = 0v 125 switching frequency vs. load current MAX16952 toc26 i load (a) frequency (mhz) 3.5 3.0 2.5 2.0 1.5 1.0 0.5 2.1 2.2 2.3 2.4 2.5 2.0 04.0 2.2mhz/5v pwm mode dips and drop test (pwm mode) MAX16952 toc27 10v/div 5v/div 0v 0v 0v 0v 10v/div 5v/div v sup 2.2mhz/5v i load = 4a v out v lx v pgood 10ms/div dips and drop test (pwm mode) MAX16952 toc28 10v/div 5v/div 0v 0v 0v 0v 10v/div 5v/div v sup 2.2mhz/3.3v i load = 4a v out v lx v pgood 10ms/div MAX16952 36v, 2.2mhz step-down controller with low operating current 8 maxim integrated typical operating characteristics (continued) (v sup = v en = 14v, c in = 47f, c out = 94f, c bias = 2.2f, c bst = 0.1f, r fosc = 13k ? , v fb = v bias , r bst = 75 ? , t a = +25c, unless otherwise noted.)
pin description pin name function 1 sup input supply voltage. sup is the input voltage to the internal linear regulator. bypass sup to pgnd with a 1f minimum value ceramic capacitor. 2 en active-high enable input. en is compatible with 5v and 3.3v logic levels. drive en logic-high to enable the output or drive en logic-low to put the controller in low-power shutdown mode. connect en to sup for always-on operation. do not leave en unconnected. 3 fosc oscillator-timing resistor input. connect a resistor from fosc to sgnd to set the oscillator freq uency from 1mhz to 2.2mhz. see the setting the switching frequency section. 4 fsync synchronization and mode selection input. connect fsync to bias to select fixed-frequency pwm mode and disable skip mode. connect fsync to sgnd to select skip mode. connect fsync to an external clock for synchronization. fsync is internally pulled down to ground with a 1m resistor. 5 sgnd signal ground. connect sgnd directly to the local ground plane. connect sgnd to pgnd at a single point. 6 comp error amplifier output. connect comp to the compensation feedback network. see the compensation design section. 7 fb feedback regulation point. connect fb to bias for a fixed 5v output voltage. in adjustable mode, connect to the center tap of a resistive divider from the output (v out ) to sgnd to set the output voltage. the fb voltage regulates to 1v (typ). 8 cs positive current-sense input. connect cs to the positive terminal of the current-sense element. figure 4 shows two different current-sensing options: 1) accurate sense with a sense resistor or 2) lossless inductor dcr sensing. MAX16952 36v, 2.2mhz step-down controller with low operating current 9 maxim integrated pin configuration MAX16952 16 tssop + bst 1 sup 15 dh 2 en 14 lx 3 fosc 13 bias 4 fsync 12 dl 5 sgnd 11 pgnd 6 comp 10 pgood 7 fb 9 top view out 8 cs ep
MAX16952 36v, 2.2mhz step-down controller with low operating current 10 maxim integrated pin description (continued) pin name function 9 out output sense and negative current-sense input. when using the internal preset 5v feedback divider (fb = bias), the controller uses out to sense the output voltage. connect out to the negative terminal of the current-sense element. 10 pgood open-drain power-good output. a logic-high voltage on pgood indicates that the output voltage is in regulation. pgood is pulled low when the output voltage is out of regulation. connect a 10k pullup resistor from pgood to the digital interface voltage. 11 pgnd power ground. connect the input and output filter capacitors negative terminals to pgnd. connect pgnd externally to sgnd at a single point. 12 dl low-side gate-driver output. dl swings from v bias to pgnd. if a resistor is needed between dl and the gate of the mosfet, contact the factory for the optimum value. 13 bias internal 5v linear regulator output. bias provides power for bias and gate drive. connect a 2.2f to 10f ceramic capacitor from bias to pgnd. 14 lx external inductor connection. connect lx to the switched side of the inductor. lx serves as the lower supply rail for the dh high-side gate driver. 15 dh high-side gate-driver output. dh swings from lx to bst. if a resistor is needed between dh and the gate of the mosfet, contact the factory for the optimum value. 16 bst boost flying capacitor connection. connect a ceramic capacitor between bst and lx. see the boost- flying capacitor selection section for details. ep exposed pad. internally connected to gr ound. connect ep to a large contiguous copper plane at sgnd potential to improve thermal dissipation. do not use as the main ground connection.
MAX16952 36v, 2.2mhz step-down controller with low operating current 11 maxim integrated functional diagram MAX16952 en ldo ref bias osc buck controller sup bst switch bst en sgnd pgood fb comp ea cs zx ug lg pwm ilim eafb ref dh lx bias pgnd dl clk fosc mode sync fsync mode cs out sgnd fbi
MAX16952 36v, 2.2mhz step-down controller with low operating current 12 maxim integrated detailed description the MAX16952 is a current-mode, synchronous pwm buck controller designed to drive logic-level mosfets. the device tolerates a wide input voltage range from 3.5v to 42v and generates an adjustable 1v to 10v or fixed 5v output voltage. this device can operate in dropout mode, making it ideal for automotive and industrial applications with undervoltage transients. the internal switching frequency is adjustable from 1mhz to 2.2mhz with an external resistor and can be synchronized to an external clock. the high switching frequency reduces output ripple and allows the use of small external components. the device operates in both fixed-frequency pwm mode and a low quiescent current skip mode. while working in skip mode, the operating current is as low as 50a. the device features an enable logic input to disable the device and reduce its shutdown current to 10a. protection features include cycle-by-cycle current limit, overvoltage detection, and thermal shutdown. the device also features integrated soft-start and a power- good monitor to help with power sequencing. supply voltage range (sup) the supply voltage range (v sup ) of the MAX16952 is com- patible to the typical automotive battery voltage range from 3.5v to 36v and can tolerate up to 42v transients. slow ramp-up of the input voltage if the input voltage (v sup ) ramps up slowly, the device operates in dropout mode until v sup is greater than the regulated output voltage. the dropout mode is detected by monitoring high-side fet on for eight clock cycles. once dropout mode is detected, the controller issues a forced low-side pulse at the rising edge of switching clock to refresh the bst capacitor. this maintains the proper bst voltage to turn on the high-side mosfet when the device is in dropout mode. system enable (en) and soft-start an enable control input (en) activates the MAX16952 from its low-power shutdown mode. en is compatible with inputs from automotive battery level down to 3.5v. the high-voltage compatibility allows en to be connected to sup, key/kl30, or the inhibit pin (inh) of a can transceiver. a logic-high at en turns on the internal regulator. once v bias is above the internal lockout level, v uvl = 3.1v (typ), the controller starts up with a 5ms fixed soft-start time. once regulation is reached, pgood goes high impedance. a logic-low at en shuts down the device. during shut- down, the internal linear regulator and gate drivers turn off. shutdown is the lowest power state and reduces the quiescent current to 10a (typ). to protect the low-side mosfet during shutdown, the step-down regulator cannot be enabled until the output voltage drops below 1.25v. an internal 30 ? pulldown switch helps discharge the output. if the en pin is tog- gled low then high, the switching regulator shuts down and remains off until the output voltage decays to 1.25v. at this point, the MAX16952 turns on using the soft-start sequence. fixed 5v linear regulator (bias) the MAX16952 has an internal 5v linear regulator to provide its own 5v bias from a high-voltage input supply at sup. this bias supply powers the gate drivers for the external n-channel mosfets and provides the power required for the analog controller, reference, and logic blocks. the bias rail needs to be stabilized by a 2.2f or greater capacitance at bias, and can provide up to 45ma (typ) total current. the linear regulator has an overcurrent threshold of approximately 100ma. in case of an overcurrent event, the current is limited to 100ma and the bias voltage starts to droop. as soon as v bias drops to 2.9v (typ), the step-down converter shuts down and the power mosfets are turned off. oscillator frequency and external synchronization the MAX16952 provides an internal oscillator adjustable from 1mhz to 2.2mhz. to set the switching frequency, connect a resistor from fosc to sgnd. see the setting the switching frequency section. the MAX16952 can also be synchronized to an external clock by connecting the external clock signal to fsync. for proper frequency synchronization, fsyncs input frequency must be at least 10% higher than the programmed internal oscillator frequency. a rising clock edge on fsync is interpreted as a syn- chronization input. if the fsync signal is lost, the inter- nal oscillator takes control of the switching rate, returning to the switching frequency set by the resistor connected to fosc. this maintains output regulation even with intermittent fsync signals. the maximum synchronizable frequency is 2.4mhz. when fsync is connected to sgnd, the device oper- ates in skip mode. when fsync is connected to bias or driven by an external clock, the MAX16952 operates in skip mode during soft-start and transitions to fixed- frequency pwm mode after soft-start is over.
MAX16952 36v, 2.2mhz step-down controller with low operating current 13 maxim integrated error detection and fault behavior several error-detection mechanisms prevent damage to the MAX16952 and the application circuit: ? overcurrent protection ? output overvoltage protection ? undervoltage lockout at bias ? power-good detection of the output voltage ? overtemperature protection of the ic overcurrent protection the MAX16952 provides cycle-by-cycle current limiting as long as the fb voltage is greater than 0.7v (i.e., 70% of the regulated output voltage). if the output voltage drops below 70% of the regulation point due to overcur- rent event, 16 consecutive current-limit events initiate restart. if the overcurrent is still present during restart, the MAX16952 shuts down and initiates restart. this automatic restart continues until the overcurrent condi- tion disappears. if the overcurrent condition disappears at any restart attempt, the device enters the normal soft-start routine. if the output is shorted through a long wire, output volt- age can fall significantly below ground before reaching the overcurrent limit. under this condition, the MAX16952 stops switching and initiates restart as soon as output drops to 20% of its regulation point. output overvoltage protection the MAX16952 features an internal output overvoltage protection. if v out increases by 13% (typ) of the intended regulation voltage, the high-side mosfet turns off and the low-side mosfet turns on. the low- side mosfet stays on until v out goes back into regu- lation. once v out is in regulation, the normal switching cycles continue. undervoltage lockout (uvlo) the bias input undervoltage lockout (uvlo) circuitry inhibits switching if the 5v bias supply (bias) is below its uvlo threshold, 3.1v (typ). if the bias voltage drops below the uvlo threshold, the controller stops switching and turns off both high-side and low-side gate drivers until the bias voltage recovers. power-good detection (pgood) the MAX16952 includes a power-good comparator with added hysteresis to monitor the step-down con- trollers output voltage and detect the power-good threshold. the pgood output is open drain and should be pulled up with an external resistor to the supply volt- age of the logic input it drives. this voltage should not exceed 6v. a 10k ? pullup resistor works well in most applications. pgood can sink up to 3ma of current while low. pgood asserts low during the following conditions: ? standby mode ? undervoltage with v out below 88% (typ) its set value ? overvoltage with v out above 113% (typ) its set value the power-good levels are measured at fb if a feed- back divider is used. if the MAX16952 is used in 5v mode with fb connected to bias, out is used as a feedback path for voltage regulation and power-good determination. overtemperature protection thermal-overload protection limits total power dissipa- tion in the MAX16952. when the junction temperature exceeds +175c (typ), an internal thermal sensor shuts down the step-down controller, allowing the ic to cool. the thermal sensor turns on the ic again after the junc- tion temperature cools by 15c and the output voltage has dropped below 1.25v (typ). a continuous overtemperature condition can cause on-/off-cycling of the device. fixed-frequency, current-mode pwm controller the MAX16952s step-down controller uses a pwm, current-mode control scheme. an internal transconduc- tance amplifier establishes an integrated error voltage. the heart of the pwm controller is an open-loop com- parator that compares the integrated voltage-feedback signal against the amplified current-sense signal plus the slope compensation ramp, which are summed into the main pwm comparator to preserve inner-loop sta- bility and eliminate inductor stair-casing. at each falling edge of the internal clock, the high-side mosfet turns on until the pwm comparator trips, the maximum duty cycle is reached, or the peak current limit is reached. during this on-time, current ramps up through the inductor, storing energy in its magnetic field and sourc- ing current to the output. the current-mode feedback system regulates the peak inductor current as a func- tion of the output-voltage error signal. the circuit acts as a switch-mode transconductance amplifier and elim- inates the influence of the output lc filter double pole. during the second half of the cycle, the high-side mosfet turns off and the low-side mosfet turns on. the inductor releases the stored energy as the current ramps down, providing current to the output. the out- put capacitor stores charge when the inductor current
MAX16952 36v, 2.2mhz step-down controller with low operating current 14 maxim integrated exceeds the required load current and discharges when the inductor current is lower, smoothing the volt- age across the load. under soft-overload conditions, when the peak inductor current exceeds the selected current limit, the high-side mosfet is turned off imme- diately. the low-side mosfet is turned on and remains on to let the inductor current ramp down until the next clock cycle. forced fixed-frequency pwm mode the low-noise forced fixed-frequency pwm mode (fsync connected to bias or an external clock) dis- ables the zero-crossing comparator, which controls the low-side switch on-time. this forces the low-side gate- driver waveform to constantly be the complement of the high-side gate-drive waveform. the inductor current reverses at light loads while dh maintains a duty factor of v out /v sup . the benefit of forced fixed-frequency pwm mode is to keep the switching frequency fairly constant. however, forced fixed-frequency pwm operation comes at a cost: the no-load 5v supply current can be up to 45ma, depending on the external mosfets and switching fre- quency. forced fixed-frequency pwm mode is most useful for avoiding audio frequency noises and improv- ing load-transient response. light-load low-quiescent operating (skip) mode the MAX16952 includes a light-load operating mode control input (fsync = sgnd) used to enable or dis- able the zero-crossing comparator. when the zero- crossing comparator is enabled, the regulator forces dl low when the current-sense inputs detect zero inductor current. this keeps the inductor from discharg- ing the output capacitor and forces the regulator to skip pulses under light-load conditions to avoid overcharg- ing the output. the lowest operating currents can be achieved in skip mode. when the MAX16952 operates in skip mode with no external load current, the overall current consump- tion can be as low as 50a. a disadvantage of skip mode is that the operating frequency is not fixed. skip-mode current-sense threshold when skip mode is enabled, the on-time of the step- down controller terminates when the output voltage exceeds the feedback threshold and when the current- sense voltage exceeds the idle-mode current-sense threshold (v cs,idle ). see figure 1. under light-load conditions, the on-time duration depends solely on the skip-mode current-sense threshold, which is 25mv (typ). this forces the controller to source a minimum amount of power with each cycle. to avoid overcharging the output, another on-time cannot begin until the output voltage drops below the feedback threshold. because the zero-crossing comparator prevents the switching regulator from sinking current, the controller must skip pulses. therefore, the controller regulates the valley of the output ripple under light-load conditions. automatic pulse-skipping crossover in skip mode, an inherent automatic switchover to pulse frequency modulation (pfm) takes place at light loads. this switchover is affected by a comparator that trun- cates the low-side switch on-time at the inductor cur- rents zero crossing. the zero-crossing comparator senses the inductor current across cs to out. once (v cs - v out ) drops below the 6mv zero-crossing, cur- rent-sense threshold, the comparator forces dl low. this mechanism causes the threshold between pulse- skipping pfm and nonskipping pwm operation to coin- cide with the boundary between continuous and discontinuous inductor-current operation (also known as the critical conduction point). the load-current level at which pfm/pwm crossover occurs, i load(skip) , is given by: the switching waveforms can appear noisy and asyn- chronous when light-loading causes pulse-skipping operation. this is a normal operating condition that results in high light-load efficiency. trade-offs in pfm noise vs. light-load efficiency is made by varying the inductor value. generally, low inductor values pro- duce a broader efficiency versus load current, while higher values result in higher full-load efficiency (assuming that the coil resistance remains constant) and less output-voltage ripple. drawbacks of using higher inductor values include larger physical size and degraded load-transient response (especially at low input-voltage levels). mosfet gate drivers (dh and dl) the dh and dl drivers are optimized for driving logic- level n-channel power mosfets. the dh high-side n- channel mosfet driver is powered by charge pumping at bst, while the dl synchronous rectifier drivers are powered directly by the 5v linear regulator (bias). an adaptive dead-time circuit monitors the dh and dl outputs and prevents the opposite-side mosfet from turning on until the other mosfet is fully off. thus, the circuit allows the high-side driver to turn on only when the dl gate driver has been turned off. similarly, it pre- vents the low-side (dl) from turning on until the dh gate driver has been turned off. ia vvv vfmhz load skip sup out out sup sw () [] = ? () 2 [ [] [] lh
MAX16952 36v, 2.2mhz step-down controller with low operating current 15 maxim integrated the adaptive driver dead-time allows operation without shoot-through with a wide range of mosfets, minimiz- ing delays and maintaining efficiency. there must be a low-resistance, low-inductance path from the dl and dh drivers to the mosfet gates for the adaptive dead- time circuits to work properly. otherwise, because of the stray impedance in the gate discharge path, the sense circuitry could interpret the mosfet gates as off while the v gs of the mosfet is still high. to minimize stray impedance, use very short, wide traces (50 mils to 100 mils wide if the mosfet is 1in from the controller). synchronous rectification reduces conduction losses in the rectifier by replacing the normal low-side schottky catch diode with a low-resistance mosfet switch. the internal pulldown transistor that drives dl low is robust, with a 2 ? (typ) on-resistance. this low on-resistance helps prevent dl from being pulled up during the fast rise time of the lx node, due to capacitive coupling from the drain to the gate of the low-side synchronous rectifier mosfet. applications with high-input voltages and long-inductive driver traces can require additional gate-to-source capacitance. this ensures that fast-ris- ing lx edges do not pull up the low-side mosfets gate, causing shoot-through currents. the capacitive coupling between lx and dl created by the mosfets gate-to-drain capacitance (c gd = c rss ), gate-to- source capacitance (c gs = c iss - c gd ), and additional board parasitic should not exceed the following mini- mum threshold: high-side gate-drive supply (bst) the high-side mosfet is turned on by closing an inter- nal switch between bst and dh. this provides the necessary gate-to-source voltage to turn on the high- side mosfet, an action that boosts the gate-drive signal above v sup . the boost capacitor connected between bst and lx holds up the voltage across the flying gate driver during the high-side mosfet on-time. the charge lost by the boost capacitor for delivering the gate charge is refreshed when the high-side mosfet is turned off and the lx node swings down to ground. when the lx node is low, an internal high- voltage switch connected between bias and bst recharges the boost capacitor to the bias voltage. see the boost-flying capacitor selection section to choose the right size of the boost capacitor. dropout behavior during undervoltage transition the controller generates a low-side pulse every eight clock cycles to refresh the bst capacitor during low- dropout operation. this guarantees that the MAX16952 operates in dropout mode during undervoltage tran- sients like cold crank. see the boost-flying capacitor selection section for more details. current limiting and current-sense inputs (cs and out) the current-limit circuit uses differential current-sense inputs (cs and out) to limit the peak inductor current. if the magnitude of the current-sense signal exceeds the current-limit threshold, the pwm controller turns off the high-side mosfet. the actual maximum load cur- rent is less than the peak current-limit threshold by an amount equal to half the inductor ripple current. therefore, the maximum load capability is a function of the current-sense resistance, inductor value, switching frequency, and duty cycle (v out /v sup ). see the current sensing section. design procedure effective input voltage range although the MAX16952 controller can operate from input supplies up to 42v and regulate down to 1v, the minimum voltage conversion ratio (v out /v sup ) might be limited by the minimum controllable on-time. for proper fixed-frequency pwm operation, the voltage conversion ratio should obey the following condition: where t on(min) is 80ns and f sw is the switching fre- quency in hz. if the desired voltage conversion does v v tf out sup on min sw > () vv c c gs th sup rss iss () > ? ? ? ? ? ? figure 1. pulse-skipping/discontinuous crossover point inductor current time 0 v out v sup f sw t on(skip) = on-time i pk i load = i pk /2
MAX16952 36v, 2.2mhz step-down controller with low operating current 16 maxim integrated not meet the above condition, then pulse skipping occurs to decrease the effective duty cycle. to avoid this, decrease the switching frequency or lower the input voltage (v sup ). setting the output voltage connect fb to bias to enable the fixed step-down con- troller output voltage (5v), set by a preset, internal resistive voltage-divider connected between the output (out) and sgnd. to achieve other output voltages between 1v to 10v, connect a resistive divider from out to fb to sgnd (figure 2). select r fb2 (fb to sgnd resistor) less than or equal to 100k ? . calculate r fb1 (out to fb resistor) with the following equation: where v fb = 1v (typ) (see the electrical characteristics table) and v out can range from 1v to 10v. setting the switching frequency the switching frequency, f sw , is set by a resistor (r fosc ) connected from fosc to sgnd. see figure 3 to select the correct r fosc value for the desired switching frequency. for example, a 2mhz switching frequency is set with r fosc = 14.3k ? . higher frequencies allow designs with lower inductor values and less output capacitance. consequently, peak currents and i 2 r losses are lower at higher switching frequencies, but core losses, gate- charge currents, and switching losses increase. inductor selection three key inductor parameters must be specified for operation with the MAX16952: inductance value (l), inductor saturation current (i sat ), and dc resistance (r dcr ). to select inductance value, the ratio of inductor peak-to-peak ac current to dc average current (lir) must be selected first. a good compromise between size and loss is a 30% peak-to-peak ripple current to average-current ratio (lir = 0.3). the switching fre- quency, input voltage, output voltage, and selected lir then determine the inductor value as follows: where v sup(min) is the minimum supply voltage, v out is the typical output voltage, and i out(max) is the maximum load current. the switching frequency is set by r fosc (see the setting the switching frequency section). the MAX16952 uses internal frequency independent slope compensation to ensure stable operation at duty cycles above 50%. use the equation below to select the inductor value: vv lh f mhz out sw [] [] [ ] % ? = 125 l vv v vfi out sup min out sup min sw out ma = ? () () () ( x x lir ) rr v v fb fb out fb 12 1 = ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? figure 2. adjustable output voltage MAX16952 r fb2 r fb1 out fb figure 3. switching frequency vs. r fosc switching frequency vs. r fosc MAX16952 toc07 r fosc (k i ) swithcing frequency (mhz) 35 30 25 20 15 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 1.0 10 40
MAX16952 36v, 2.2mhz step-down controller with low operating current 17 maxim integrated however, if it is necessary, higher inductor values can be selected. the exact inductor value is not critical and can be adjusted to make trade-offs among size, cost, efficien- cy, and transient response requirements. table 1 shows a comparison between small and large inductor sizes. the minimum practical inductor value is one that causes the circuit to operate at the edge of critical conduction (where the inductor current just touches zero with every cycle at maximum load). inductor val- ues lower than this grant no further size-reduction benefit. the optimum operating point is usually found between 25% and 45% ripple current. when pulse skipping (fsync low and light loads), the inductor value also determines the load-current value at which pfm/pwm switchover occurs. for the selected inductance value, the actual peak-to- peak inductor ripple current ( ? i inductor ) is defined by: where ? i inductor is in ma, l is in h, and f sw is in khz. the core must be large enough not to saturate at the peak inductor current (i peak ): transient response the inductor ripple current also impacts transient response performance, especially at low v sup - v out differentials. low inductor values allow the inductor cur- rent to slew faster, replenishing charge removed from the output filter capacitors by a sudden load step. the total output voltage sag is the sum of the voltage sag while the inductor is ramping up and the voltage sag before the next pulse can occur: where d max is the maximum duty factor (see the electrical characteristics table), l is the inductor value in h, c out is the output capacitor value in f, t is the switching period (1/f sw ) in s, and ? t equals (v out /v sup ) t when in fixed-frequency pwm mode, or l 0.2 i max /(v sup - v out ) when in skip mode. the amount of overshoot (v soar ) during a full-load to no- load transient due to stored inductor energy can be cal- culated as: current sensing for the most accurate current sensing, use a current- sense resistor (r sense ) between the inductor and the output capacitor. connect cs to the inductor side of r sense , and out to the capacitor side. size r sense such that its maximum current (i oc ) induces a voltage of v limit (68mv minimum) across r sense . if a higher voltage drop across r sense must be tolerated, divide the voltage across the sense resistor with a voltage-divider between cs and out to reach v limit (68mv minimum). the current-sense method (figure 4) and magnitude determine the achievable current-limit accuracy and power loss. typically, higher current-sense limits provide tighter accuracy, but also dissipate more power. for the best current-sense accuracy and over- current protection, use a 1% tolerance current-sense resistor with low parasitic inductance between the inductor and output as shown in figure 4a. alternatively, high-power applications that do not require highly accurate current-limit protection can reduce the overall power dissipation by connecting a series rc circuit across the inductor (figure 4b) with an equivalent time constant: r r rr r cshl dcr = + ? ? ? ? ? ? 2 12 v il cv soar load max out out ? () () 2 2 v li cvd v sag load max out sup max out = ? () () ? () () 2 2 + + ??? () itt c load max out () ii i peak load max inductor =+ ? () 2 ?= ? () i vv v vfl inductor out sup out sup sw inductor size smaller larger lower price smaller ripple smaller form factor higher efficiency faster load response larger fixed-frequency range in skip mode table 1. inductor size comparison
MAX16952 36v, 2.2mhz step-down controller with low operating current 18 maxim integrated and: where r cshl is the required current-sense resistor and r dcr is the inductors series dc resistance. use the typical inductance and r dcr values provided by the inductor manufacturer. carefully observe the pcb layout guidelines to ensure the noise and dc errors do not corrupt the differential current-sense signals seen by cs and out. place the sense resistor close to the ic with short, direct traces, making a kelvin-sense connection to the current-sense resistor. r l crr dcr eq =+ ? ? ? ? ? ? 1 1 1 2 figure 4. current-sense configurations MAX16952 dh dl l nh nl lx cs out dl gnd r sense c out c in input (v in ) a) output series resistor sensing MAX16952 dh dl l nh nl lx cs out dl gnd r dcr r cshl = ( ) r dcr r2 r1 + r2 r1 r2 c eq inductor c out c in input (v in ) b) lossless inductor sensing r dcr = [ + ] l c eq 1 r1 1 r2
MAX16952 36v, 2.2mhz step-down controller with low operating current 19 maxim integrated input capacitor the input filter capacitor reduces peak currents drawn from the power source and reduces noise and voltage ripple on the input caused by the circuits switching. the input capacitor rms current requirement (i rms ) is defined by the following equation: i rms has a maximum value when the input voltage equals twice the output voltage (v sup = 2v out ), so i rms(max) = i load(max) /2. choose an input capacitor that exhibits less than +10c self-heating temperature rise at the rms input current for optimal long-term reliability. the input-voltage ripple comprises ? v q (caused by the capacitor discharge) and ? v esr (caused by the esr of the capacitor). use low-esr ceramic capacitors with high-ripple current capability at the input. assume the contribution from the esr and capacitor discharge is equal to 50%. calculate the input capacitance and esr required for a specified input voltage ripple using the following equations: where: and: where: output capacitor the output filter capacitor must have low enough esr to meet output ripple and load-transient requirements, yet have high enough esr to satisfy stability require- ments. the output capacitance must be high enough to absorb the inductor energy while transitioning from full- load to no-load conditions without tripping the overvolt- age fault protection. when using high-capacitance, low-esr capacitors, the filter capacitors esr domi- nates the output-voltage ripple. the size of the output capacitor depends on the maximum esr required to meet the output-voltage ripple (v ripple(p-p) ) specifica- tions: in skip mode, the inductor current becomes discontinu- ous, with the peak current set by the skip-mode current- sense threshold (v skip = 32mv, typ). in skip mode, the no-load output ripple can be determined as follows: the actual capacitance value required relates to the physical size needed to achieve low esr, as well as to the chemistry of the capacitor technology. thus, the capacitor is usually selected by esr and voltage rating rather than by capacitance value. when using low-value filter capacitors, such as ceramic capacitors, size is usually determined by the capacity needed to prevent v sag and v soar from causing problems during load transients. generally, once enough capacitance is added to meet the overshoot requirement, undershoot at the rising load edge is no longer a problem (see the v sag and v soar equations in the transient response section). however, low-value filter capacitors typically have high-esr zeros that can affect the overall stability. compensation design the MAX16952 uses an internal transconductance error amplifier with its inverting input and its output available to the user for external frequency compensation. the output capacitor and compensation network determine the loop stability. the inductor and the output capacitor are chosen based on performance, size, and cost. additionally, the compensation network optimizes the control-loop stability. the controller uses a current-mode control scheme that regulates the output voltage by forcing the required current through the external inductor. the MAX16952 uses the voltage drop across the dc resistance of the inductor or the alternate series current-sense resistor to measure the inductor current. current-mode control eliminates the double pole in the feedback loop caused v v esr r ripple p p skip sense () ? = v esr i lir ripple p p load max () ( ) ? = d v v out sup = c idd vf in out qsw = ? () ? 1 ?= ? () i vv v vfl l sup out out sup sw esr v i i in esr out l = ? + ? 2 ii vv v v rms load max out sup out sup = ? () ()
MAX16952 36v, 2.2mhz step-down controller with low operating current 20 maxim integrated by the inductor and output capacitor, resulting in a smaller phase shift and requiring less elaborate error- amplifier compensation than voltage-mode control. a simple single-series resistor (r c ) and capacitor (c c ) are required to have a stable, high-bandwidth loop in applications where ceramic capacitors are used for output filtering (figure 5). for other types of capacitors, due to the higher capacitance and esr, the frequency of the zero created by the capacitance and esr is lower than the desired closed-loop crossover frequen- cy. to stabilize a nonceramic output capacitor loop, add another compensation capacitor (c f ) from comp to sgnd to cancel this esr zero. the basic regulator loop is modeled as a power modu- lator, output feedback divider, and an error amplifier. the power modulator has a dc gain set by g mc r load , with a pole and zero pair set by r load , the out- put capacitor (c out ), and its esr. the following equa- tions determine the approximate value for the gain of the power modulator (gain mod(dc) ), neglecting the effect of the ramp stabilization. ramp stabilization is necessary when the duty cycle is above 50% and is internally and automatically done for the MAX16952: where r load = v out /i out(max) in ? , f sw is the switch- ing frequency in mhz, l is the output inductance in h, and g mc = 1/(a v_cs r dc ) in s. a v_cs is the voltage gain of the current-sense amplifier and is typically 11v/v. r dc is the dc-resistance of the inductor or the current-sense resistor in ? . in a current-mode step-down converter, the output capacitor, its esr, and the load resistance introduce a pole at the following frequency: the output capacitor and its esr also introduce a zero at: when c out is composed of n identical capacitors in parallel, the resulting c out = n c out(each) , and esr = esr (each) /n. note that the capacitor zero for a paral- lel combination of like capacitors is the same as for an individual capacitor. the feedback voltage-divider has a gain of gain fb = v fb /v out , where v fb is 1v (typ). the transconductance error amplifier has a dc gain of gain ea(dc) = g m,ea r out,ea , where g m,ea is the error amplifier transconductance, and r out,ea is the output resistance of the error amplifier. use g m,ea of 2500s (max) and r out,ea of 30m ? (typ) for compen- sation design with the highest phase margin. a dominant pole (f dpea ) is set by the compensation capacitor (c c ), the compensation resistor (r c ), and the amplifier output resistance (r out,ea ). a zero (f zea ) is set by the compensation resistor (r c ) and the compen- sation capacitor (c c ). there is an optional pole (f pea ) set by c f and r c to cancel the output capacitor esr zero if it occurs near the crossover frequency (f c , where the loop gain equals 1 (0db)). thus: the loop-gain crossover frequency (f c ) should be set below 1/5 the switching frequency and much higher than the power-modulator pole (f pmod ): the total loop gain as the product of the modulator gain, the feedback voltage-divider gain, and the error amplifier gain at f c should be equal to 1. so: for the case where f zmod is greater than f c : gain g r gain gain ea fc mea c mod fc mod dc () () = = , () f f f pmod c gain v v gain mod fc fb out ea fc () () = 1 ff f pmod c sw << 5 f cr r f cr f dpea couteac zea cc pea = + () = 1 2 1 2 , = = 1 2 cr fc f esr c zmod out = 1 2 f c rfl rfl esr pmod out load sw load sw = + () + 1 2 ? ? ? ? ? ? ? ? ? gain g rfl rfl mod dc mc load sw load sw () ? + ()
MAX16952 36v, 2.2mhz step-down controller with low operating current 21 maxim integrated therefore: solving for r c : set the error-amplifier compensation zero formed by r c and c c (f zea ) at the f pmod . calculate the value of c c as follows: if f zmod is less than 5 x f c , add a second capacitor, c f , from comp to sgnd and set the compensation pole formed by r c and c f (f pea ) at the f zmod . calculate the value of c f as follows: as the load current decreases, the modulator pole also decreases; however, the modulator gain increases accordingly and the crossover frequency remains the same. for the case where f zmod is less than f c : the power-modulator gain at f c is: the error-amplifier gain at f c is: therefore: solving for r c : set the error-amplifier compensation zero formed by r c and c c at the f pmod (f zea = f pmod ): if f zmod is less than 5 f c , add a second capacitor c f from comp to sgnd. set f pea = f zmod and calculate c f as follows: mosfet selection the MAX16952s controller drives two external logic- level n-channel mosfets as the circuit switch ele- ments. the key selection parameters to choose these mosfets include: ? on-resistance (r ds(on) ) ? maximum drain-to-source voltage (v ds(max) ) ? minimum threshold voltage (v th(min) ) ? total gate charge (q g ) ? reverse-transfer capacitance (c rss ) ? power dissipation c rf f czmod = 1 2 c fr c mod c = 1 2 2 r vf g v gain f c out c mea fb mod f zmod c = () , gain v v gr f f mod fc fb out mea c zmod c () = , 1 gain g r f f ea fc mea c zmod c () = , gain gain f f mod fc mod dc pmod zmod () () = c fr f zmod c = 1 2 c fr c pmod c = 1 2 r v g v gain c out mea fb mod fc = () , gain v v gr mod fc fb out mea c () = , 1 figure 5. compensation network r1 r c r2 c c c f v out v ref g m comp
MAX16952 36v, 2.2mhz step-down controller with low operating current 22 maxim integrated both n-channel mosfets must be logic-level types with guaranteed on-resistance specifications at v gs = 4.5v. ensure that the conduction losses at minimum input voltage do not exceed mosfet package thermal limits or violate the overall thermal budget. also, ensure that the conduction losses, plus switching losses at the maximum input voltage, do not exceed package ratings or violate the overall thermal budget. the MAX16952s dl gate driver must drive the low-side mosfet (nl). in particular, check that the dv/dt caused by the high-side mosfet (nh) turning on does not pull up the nl gate through its drain-to-gate capacitance. this is the most frequent cause of cross-conduction problems. gate-charge losses are dissipated by the driver and do not heat the mosfet. therefore, if the drive current is taken from the internal ldo regulator, the power dissi- pation due to drive losses must be checked. both mosfets must be selected so that their total gate charge is low enough; therefore, bias can power both drivers without overheating the ic: p drive = (v sup - v bias ) q g_total f sw where q g_total is the sum of the gate charges of both mosfets. boost-flying capacitor selection the bootstrap capacitor stores the gate voltage for the internal switch. its size is constrained by the switching frequency and the gate charge of the high-side mosfet. ideally the bootstrap capacitance should be at least nine times the gate capacitance: this results in a 10% voltage drop when the gate is driven. however, if this value becomes too large to be recharged during the minimum off-time, a smaller capacitor must be chosen. during recharge, the internal bootstrap switch acts as a resistor, resulting in an rc circuit with the associated time constants. two s (time constants) are necessary to charge from 90% to 99%. the maximum allowable capacitance is, therefore: the minimum off-time allowed for the MAX16952 is 100ns (typ). if eight consecutive 100ns pulses are detected, the lsfet is forced on for one-half clock cycle minimum. this is to ensure that the charge on the boost capacitor is replenished fully. the worst case operation is when the MAX16952 is close to dropout, but not fully in dropout with no load on the output. this means consecutive minimum off-time pulses are < 8. in this scenario, ensure that the amount of charge lost per cycle is replenished in 100ns. in some applications external boost resistor is added to slow down the turn-on time for the hsfet. this causes an extra voltage drop on the bst capacitor per cycle and can require a parallel boostrap diode. let us assume: q g = total gate charge for hsfet q bst = bst charge lost per cycle v l = bias voltage = 5v (typ) v bst = bst voltage (bst - lx) r bst_ext = external boost resistor used (connected between bst capacitor and bst pin) r bst = internal boost switch resistance = 5 ? (typ) with the above set of parameters ensure that: q bst > q g for every 100ns minimum off-time q bst = (v l - v bst )/(r bst_ext + r bst ) x 100ns the threshold voltage (v th ) of the external hsfet used determines the v l - v bst number. if 3v is the external hsfet threshold voltage, v l - v bst = 2v. now, if q bst > q g is not satisfied, an external parallel bootstrap schottky diode is required. applications information pcb layout guidelines make the controller ground connections as follows: cre- ate a small analog ground plane near the ic by using any of the pcb layers. connect this plane to sgnd and use this plane for the ground connection for the sup bypass capacitor, compensation components, feed- back dividers, and fosc resistor. if possible, place all power components on the top side of the board and run the power stage currents, espe- cially large high-frequency components, using traces or copper fills on the top side only, without adding vias. on the top side, lay out a large pgnd copper area for the output, and connect the bottom terminals of the high-frequency input capacitors, output capacitors, and the source terminals of the low-side mosfet to that area. c t r bst max off min bst max () () () = 2 c q v bst typ g bias () = 9
MAX16952 36v, 2.2mhz step-down controller with low operating current 23 maxim integrated figure 6. typical operating circuit for v out = 5v MAX16952 r8 13k ? 1% r2 10k ? d2 bias fb out c2 47 f 50v fosc fsync sgnd r5 7.5k ? r1 51.1k ? 1% r3 0.015 ? 1% comp c9 3300pf c8 open c7 2.2 f c1 0.1 f c11 4.7 f 50v c4 0.1 f sup bst n2 fds8449 d1 b360b n1 fds8449 pgnd dl l1 1.5 h lx v out 5v 6 4 3 pgood 10 5 v l_in en 2 v en 1 v bat 5.5v to 36v connect fsync to bias for fixed-frequency pwm mode. connect fsync to sgnd for skip mode. the MAX16952 can work down to 3.5v. 7 13 c6 47 f 6.3v c5 47 f 6.3v 9 11 12 14 cs 8 16 dh 15 then, make a star connection of the sgnd plane to the top copper pgnd area with few vias in the vicinity of the source terminal sensing. do not connect pgnd and sgnd anywhere else. refer to the MAX16952 evalua- tion kit data sheet for guidance. keep the power traces and load connections short, especially at the ground terminals. this practice is essential for high efficiency and jitter-free operation. use thick copper pcbs (2oz vs. 1oz) to enhance efficiency. place the controller ic adjacent to the synchronous rectifier mosfet (nl) and keep the connections for lx, pgnd, dh, and dl short and wide. use multiple small vias to route these signals from the top to the bottom side. the gate current traces must be short and wide, measuring 50 mils to 100 mils wide if the low-side mosfet is 1in from the controller ic. connect the pgnd trace from the ic close to the source terminal of the low-side mosfet. route high-speed switching nodes (bst, lx, dh, and dl) away from the sensitive analog areas (fosc, comp, and fb). group all sgnd-referred and feed- back components close to the ic. keep the fb and compensation network nets as small as possible to pre- vent noise pickup. chip information process: bicmos package information for the latest package outline information and land patterns (foot- prints), go to www.maximintegrated.com/packages . note that a +, #, or - in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. package type package code outline no. land pattern no. 16 tssop-ep u16e+3 21-0108 90-0120
MAX16952 36v, 2.2mhz step-down controller with low operating current maxim integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim integr ated product. no circuit patent licenses are implied. maxim integrated reserves the right to change the circuitry and specifications without notice at any time . the parametric values (min and max limits) shown in the electrical characteristics table are guaranteed. other parametric values quoted in this data sheet are provided for guidance. 24 ________________________________ maxim integrated 160 rio robles, san jose, ca 95134 usa 1-408-601-1000 ? 2012 maxim integrated products, inc. maxim integrated and the maxim integrated logo are trademarks of maxim integrated products , inc. revision history revision number revision date description pages changed 0 3/11 initial release 1 10/12 changed v out limit to 10v 1, 2, 12, 16

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